A simple DC-Link Voltage Balancing Strategy for NPC Three-level Inverters
- Authors: Foti S.; Khan H.H.; Testa A.; Di Tommaso A.O.; Miceli R.; Nevoloso C.
- Publication year: 2023
- Type: Contributo in atti di convegno pubblicato in volume
- Key words: 3-Level NPC; Capacitor voltage balancing; Pulse Width Modulation (PWM); Total Harmonic Distortion; Two-level inverters (TLIs)
- OA Link: http://hdl.handle.net/10447/624517
Abstract
Three-level neutral point clamped PWM inverters overcome some limitations of two-level inverters in medium voltage applications, leading to lower device ratings and greater efficiency. However, they are burdened by an intrinsic drawback of the neutral point clamped structure, which causes, under some operating conditions, a voltage imbalance of the DC link capacitors. In this paper, such an issue is faced on a system driven by a dual-carrier PWM strategy through a simple hysteretic control. The proposed technique features a very low computational burden and does not need additional power circuits or sensors. It is first presented theoretically, then its performance is evaluated through simulations.